Modified JPEG XS Codec Reduces Mobile Display Power by 4.7%
Researchers at the Silesian University of Technology have designed a low-power, visually lossless JPEG XS frame buffer codec optimized for on-chip display systems. Implemented on an AMD Artix UltraScale+ FPGA, the proposed design features a simplified non-standard Golomb-Rice entropy coding mode that reduces logic utilization by 28% and total codec power consumption by 4.7% compared to the standard JPEG XS precinct mode.
Key Takeaways
- Implementation on AMD Artix UltraScale+ xcau15p FPGAs achieved a 28% reduction in Look-Up Table (LUT) utilization compared to standard JPEG XS.
- The 11:1 compression ratio maintains a Peak Signal-to-Noise Ratio (PSNR) of 40.20 dB, meeting visually lossless requirements.
- Total codec power consumption dropped by 44 mW, a 4.7% improvement over the standard precinct mode at 200 MHz.
- The codec targets memory bandwidth bottlenecks between GPUs and display units in smartphones and AR headsets.
Why It Matters
The shift toward high-resolution, high-refresh-rate mobile displays has made on-chip memory bandwidth a primary battery drain. By optimizing the JPEG XS entropy coding path specifically for closed systems, manufacturers can reduce hardware footprints and thermal loads in compact form factors like AR glasses. This technical refinement signals a move toward application-specific modifications of mezzanine codecs to bypass the overhead of full standards compliance when interoperability isn't required. Watch for whether mobile SoC vendors adopt these non-standard modes in proprietary silicon to gain marginal battery life advantages over competitors using off-the-shelf IP cores.
Additional Context
The push for energy-efficient mezzanine compression arrives as the industry grapples with the power demands of 8K and high-frame-rate mobile video. Per a June 2024 report from the Fraunhofer Institute, JPEG XS has become the preferred standard for low-latency transmission in professional media workflows due to its ability to handle multi-gigabit streams with sub-millisecond lag. However, application at the chip level—specifically for frame buffer compression—requires even tighter optimizations than those found in standard broadcast gear. The IEEE recently noted in a May 2025 technical review that memory traffic accounts for up to 30% of total system power in modern mobile SOCs, making intra-chip compression a critical theater for hardware efficiency gains. Simultaneously, the competitive landscape for specialized video silicon is shifting toward high-end FPGA adoption for prototyping. Per AMD's Q1 2026 technical brief, the Artix UltraScale+ series has seen increased integration in edge-AI and mobile display controllers due to its high I/O bandwidth and relatively low thermal profile. Other industry players, such as IntoPIX, have also been pushing the boundaries of JPEG XS by introducing 'TicoXS' variants that target 8K 120fps workflows. This Silesian University research builds upon this trend by proving that stripping away standard precinct headers in favor of simplified entropy coding provides a viable path for internal chip architectures where strict ISO/IEC 21122 compliance is less critical than milliwatt savings.
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