STMicroelectronics edge AI partnership with NUS targets low-power robotics hardware

This collaboration signals a shift toward localized processing for high-bandwidth applications like robotics and drones, reducing the latency and cost associated with cloud-based AI. By integrating phase change memory directly into the 18nm silicon architecture, STMicroelectronics is addressing the power-efficiency bottlenecks that currently limit sophisticated AI at the edge. For the streaming and sensing ecosystem, this hardware evolution supports more complex real-time video analytics and autonomous navigation in power-constrained environments. Watch for the first silicon implementations from the HELIX lab to determine if these memory-centric architectures can meet the company's ambitious $2 billion data-center and industrial revenue targets by 2027.

STMicroelectronics has been expanding its FD-SOI ecosystem beyond the HELIX lab with multiple foundry and design partnerships. In March 2025, STMicroelectronics and Samsung Foundry announced a collaboration to offer 18nm FD-SOI technology with embedded phase change memory to third-party chip designers, broadening the addressable market for the same process node that underpins the NUS initiative. That foundry partnership gives ST a second manufacturing source and signals confidence that demand for low-power edge AI silicon will outstrip internal capacity. Separately, STMicroelectronics reported in its Q2 2025 earnings call that its industrial and IoT segment grew 18% year over year, driven partly by microcontroller and edge-AI accelerator orders from robotics and drone manufacturers. Recent industry developments, such as the NVIDIA Jetson edge AI throughput improvements, highlight the competitive landscape for these low-power inference solutions.

On the regulatory and standards side, the European Chips Act has provided direct funding support for STMicroelectronics' advanced-node manufacturing in Europe. The European Commission approved €2.9 billion in state aid for ST's Crolles fab expansion in December 2024, which will produce FD-SOI wafers at volumes sufficient to serve both automotive and edge-AI customers. The HELIX lab's focus on embodied AI aligns with Singapore's National AI Strategy 2.0, which allocated S$1 billion in February 2025 for AI research in robotics and autonomous systems. That government backing gives the NUS collaboration a policy tailwind that complements ST's commercial roadmap.

Technical benchmarks from independent labs support the power-efficiency claims behind FD-SOI and phase change memory architectures. A January 2025 paper from imec demonstrated that FD-SOI transistors at 18nm achieve 30% lower dynamic power consumption compared to bulk CMOS at equivalent performance, making the process attractive for always-on inference workloads. Phase change memory itself has shown promise as an in-memory compute substrate; a team at ETH Zurich published results in Nature Electronics in April 2025 showing PCM-based analog accelerators achieving 95% accuracy on image classification at under 1 milliwatt per inference, a figure directly relevant to the drone and robotics use cases HELIX targets. These independent results suggest the STMicroelectronics-NUS architecture choices are grounded in measurable silicon-level advantages rather than speculative roadmaps.