intoPIX launches MIPI-to-Ethernet bridge for sub-1ms RAW sensor streaming
intoPIX has unveiled a new MIPI-to-Ethernet FPGA Bridge designed to capture RAW Bayer data from MIPI CSI-2 sensors, compress it using JPEG XS RAW, and stream it over Gigabit Ethernet with under 1ms latency. This solution aims to simplify the evaluation and deployment of MIPI sensors for various industrial applications by offering long-reach connectivity, bandwidth reduction, and ultra-low latency. The FPGA-based board supports standard Gigabit Ethernet, PoE, and is sensor-agnostic, with software decoding available on CPU and GPU platforms.
Key Takeaways
- Delivers end-to-end latency below 0.001 seconds for real-time sensor processing
- Preserves RAW Bayer data fidelity at compression ratios up to 16:1
- Sensor-agnostic architecture supports 1 to 4 lanes of MIPI CSI-2 input
- Integrates JPEG XS RAW compression directly within a Lattice FPGA platform
- Supports software decoding on both CPU and GPU platforms for distributed compute
Why It Matters
The immediate implication is a bypass of MIPI's traditional short-reach cable limitations, allowing sensors to be placed far from central compute units without the overhead of heavy-duty specialized cabling. In the broader ecosystem, this shifts machine vision and automotive ADAS architectures away from proprietary SerDes links toward standard, interoperable Ethernet. By processing JPEG XS RAW directly on the FPGA, developers can maintain high-fidelity training data for AI models while drastically lowering hardware storage costs. Watch for increased adoption in zonal automotive architectures where centralized processing of distributed sensors is currently a bandwidth bottleneck.
Additional Context
The launch of the intoPIX MIPI-to-Ethernet bridge coincides with the finalization of the third edition of the JPEG XS standard (ISO/IEC 21122), which was published in early 2025. Per the JPEG Committee and intoPIX (January 2025), this latest edition introduced Temporal Decorrelation Coding (TDC) to improve compression efficiency for screen and overlay content, further solidifying the codec's role in low-latency IP workflows beyond standard video. In June 2026, the European Machine Vision Association (EMVA) officially incorporated JPEG XS into the GenICam framework, an industry milestone that ensures the compression technology is now a first-class citizen in the standard interface used by industrial camera manufacturers worldwide. Simultaneous developments in the automotive sector highlight the growing demand for such bridging solutions. Per Dataintelo (April 2026), the market for MIPI CSI-2 camera modules is projected to reach $8.7 billion by 2034, with a 9.6% CAGR starting in 2026. This growth is driven by the shift toward software-defined vehicles and the obsolescence of legacy LVDS interfaces. Industry partners like dSPACE have already begun integrating intoPIX's TicoRAW (the underlying technology for JPEG XS RAW) into high-performance data logging systems as of early 2026, targeting the massive data volumes generated by modern ADAS and autonomous driving tests. Furthermore, the hardware ecosystem supporting these standards is expanding through partnerships with FPGA leaders. Per Lattice Semiconductor (December 2025), new low-power FPGA platforms like the Avant and Nexus families are now optimized for these specific vision bridging tasks. By combining these power-efficient chips with lightweight compression, manufacturers are addressing the thermal and power constraints of edge-AI and UAV applications. In June 2026, Vadzo Imaging also noted that while MIPI remains the preferred interface for low-latency onboard AI, bridges like intoPIX's are essential for overcoming board-level signaling distance limits in large-scale industrial and aerial deployments.
Read full article at intopix.com
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