HardwareProduct LaunchJune 25, 2026

IBM's nanostack architecture pushes transistor density past 1nm threshold

IBM has unveiled a new sub-1 nanometer chip node featuring a novel nanostack architecture, promising up to 50% higher performance or 70% greater energy efficiency. The technology targets scaling infrastructure for generative AI and cloud computing over the next five years, with manufacturing partnerships yet to be announced.

Key Takeaways

Nanostack architecture stacks transistors in a staggered layout across two wafers connected by dielectric bonding, nearly doubling density versus IBM's 2 nm node
Transistors use three nanosheets each 5 nm thick (~15 atoms), spaced 9 nm apart — layers deposited atom by atom, per VP Huiming Bu
SRAM scaling improves 40%, directly addressing on-chip memory bottlenecks in AI inference workloads
IBM targets commercial deployment within five years; manufacturing partners for the sub-1nm node have not yet been named
All three major foundries — Intel, Samsung, and TSMC — are already in mass production of chips using IBM's 2 nm nanosheet technology

Why It Matters

For streaming infrastructure operators, the sub-1nm node targets the compute and energy cost curve underpinning generative AI and cloud workloads — the same workloads driving video encoding, recommendation, and content generation pipelines. IBM's 40% SRAM scaling improvement directly addresses the on-chip memory bottleneck that limits AI inference throughput, where larger models push latency-sensitive streaming workloads. The five-year commercial timeline means this won't affect near-term hardware roadmaps, but which foundries adopt nanostack will shape the data center silicon that streaming platforms depend on. Watch for IBM's manufacturing partner announcements — particularly whether Rapidus extends the collaboration beyond 2nm or whether TSMC, Samsung, or Intel license the architecture.

Additional Context

IBM's announcement arrives as the three major foundries are ramping 2nm production. TSMC began volume production of its N2 process in Q4 2025 at Fab 20 in Hsinchu, with Apple and AMD as initial customers, per industry reporting confirmed on TSMC's Q1 2026 earnings call. Samsung Foundry's SF2 process entered limited production in late 2025, though yields have reportedly lagged TSMC's. Intel's 18A node — a 2nm-class process using RibbonFET transistors with PowerVia backside power delivery — began production in Q1 2026 on Panther Lake.

IBM's manufacturing partner Rapidus secured 267.6 billion yen (approximately $1.7 billion) in funding from the Japanese government and 32 private-sector companies in February 2026, targeting 2nm mass production by 2027 at its IIM-1 foundry in Chitose, Hokkaido. IBM has been providing 2nm manufacturing expertise to Rapidus and plans to open a new office in Chitose to support the collaboration, per TrendForce reporting in February 2026. Japan's NEDO approved Rapidus' FY2026 budget in April 2026, covering both front-end wafer processes and back-end chiplet packaging development.

IBM's nanostack is not the only CFET (complementary field-effect transistor) architecture in development. Per MIT Technology Review (June 2026), Intel, Samsung, TSMC, and Belgian research lab Imec are all investigating CFET approaches. IBM's design distinguishes itself by staggering transistors across layers rather than stacking them directly atop one another, which the company says simplifies wiring. Dan Hutcheson, vice chair of TechInsights, told MIT Technology Review the work "puts another 10, 15 years on the roadmap." The Register (June 2026) noted that Intel discussed 3D transistor stacking as early as 2023 and Huawei has a similar concept called LogicFolding, though neither has reached production.

Read full article at fastcompany.com