Orthogone Technologies has launched an ultra-low-latency FPGA IP portfolio designed for AMD UltraScale+ and Versal platforms. The suite includes Ethernet MAC/PCS, TCP/UDP offload engines, and PCIe DMA controllers, targeting compute-intensive applications like high-performance networking and communications.
This launch provides streaming infrastructure engineers with proven tools to minimize jitter and latency at the hardware level. By moving protocol logic from the host CPU to FPGA hardware, platforms can achieve higher throughput and more predictable performance for real-time data delivery. As streaming services move toward more interactive and low-latency applications, offloading network stacks becomes a critical requirement for maintaining resource efficiency. This shift allows for more dense compute configurations in data centers by freeing up CPU cycles for application-level tasks. Watch for adoption rates among CDN providers and live-streaming hardware manufacturers seeking to integrate these deterministic networking cores into their next-generation appliances.
The integration of private 5G production in modern broadcast environments further highlights the industry's push toward hardware-accelerated, low-latency workflows. For those managing complex IP transitions, Arkona technologies IBC 2026 showcase offers additional insight into multidisciplinary engineering approaches. Recent ST 2110 control room upgrades further demonstrate the practical application of these high-speed networking standards, while SDI remains primary infrastructure for many organizations navigating the shift to IP.
Orthogone Technologies has launched a new FPGA IP portfolio for AMD UltraScale+ and Versal platforms. This suite of networking cores offloads Layer 2 through Layer 4 processing to FPGA hardware, enabling deterministic sub-microsecond latency. This is critical for streaming services needing to minimize jitter and maximize resource efficiency in data centers.
The portfolio is designed for AMD UltraScale+ and Versal platforms, with reference designs available for AMD Alveo boards.
It offloads Layer 2 through Layer 4 network processing from the host CPU to FPGA logic, achieving deterministic sub-microsecond latency and minimizing jitter.
The IP portfolio supports Ethernet line rates of 1G, 10G, 25G, 40G, and 100G, with optional Reed-Solomon FEC.
The kit includes Ethernet MAC/PCS, TCP/UDP offload engines, a PCIe circular-buffer DMA controller, encrypted RTL source, Linux driver stacks, and reference designs.
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