Marvell Technology has confirmed a quarterly dividend while advancing its 2nm optical interconnect roadmap for AI data centers and launching the Azure Payment HSM v2 service. The company also expanded its silicon-germanium manufacturing capacity through a multi-year agreement with GlobalFoundries to support future optical connectivity needs.
The shift toward 2nm manufacturing and 1.6T ZR connectivity addresses the critical throughput bottlenecks currently facing AI-heavy data center architectures. By locking in silicon-germanium capacity with GlobalFoundries, Marvell is insulating its roadmap from the supply volatility that has previously hampered high-speed optical deployments. For the streaming ecosystem, these hardware advancements provide the necessary backbone for the massive compute and low-latency delivery required by generative AI and high-resolution video processing. Industry observers should monitor the October 6 investor day in New York for specific revenue guidance regarding the 2nm product pipeline.
Marvell Technology is accelerating its 2nm optical interconnect roadmap to resolve bandwidth bottlenecks in AI-driven data centers. By securing a silicon-germanium manufacturing agreement with GlobalFoundries, the company aims to stabilize its supply chain for 1.6T ZR and 800G ZR+ solutions, ensuring the infrastructure necessary for high-resolution video and generative AI.
Product sampling for the 2nm optical components is scheduled for late 2026, with volume production expected to begin in the second half of 2027.
The agreement provides expanded silicon-germanium capacity at GlobalFoundries' Vermont facility to support the production of pluggable transceivers and co-packaged optics, helping to stabilize Marvell's supply chain.
Marvell collaborated with Microsoft and Utimaco to launch the Azure Payment HSM v2, which provides cloud-based security services in the Western U.S. and Europe.
The shift to 2nm manufacturing and 1.6T ZR connectivity addresses critical throughput bottlenecks in AI-heavy data center architectures, providing the backbone required for massive compute and low-latency delivery.
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