Chips&Media launches CFrame60 for low-latency frame compression
Chips&Media has launched CFrame60, a new frame compression hardware IP designed to address bandwidth and memory challenges in imaging, video, AI, and display applications. CFrame60 offers both lossless and lossy compression, supports flexible pixel ordering (raster-scan and block-based), and includes random access capabilities for efficient memory workflows. The IP is optimized for low-latency operations and targets various hardware components like ISP pipelines, NPUs, VPUs, GPUs, and display subsystems.
Key Takeaways
- CFrame60 supports both lossless and lossy compression for ISP pipelines, NPUs, VPUs, GPUs, and display subsystems.
- The IP handles raster-scan and block-based pixel ordering, which can remove line-buffer stages that exceed 160KB in 4K YUV422 10-bit systems.
- CFrame60R adds random access at arbitrary Access Units and partial updates for localized image regions.
- A single core supports 4K 60fps at 250MHz to 450MHz, while eight cores scale to 8K 120fps or 16K 30fps.
- Supported formats include YUV400, YUV420, YUV422, YUV444, RGB, and Bayer, with 8-bit to 16-bit bit depths.
Why It Matters
CFrame60 tackles a concrete bottleneck in SoC design: bandwidth and memory pressure in imaging, video, AI, and display pipelines. By supporting both raster-scan and block-based ordering, it avoids SRAM-heavy line conversion stages that can exceed 160KB in 4K YUV422 10-bit systems. That matters across ISP, NPU, VPU, GPU, and display blocks, where latency and power are tightly constrained. The most useful signal to watch next is how Chips&Media’s CFrame60C, CFrame60V, and CFrame60R variants map into specific customer workflows, especially the random-access features in CFrame60R.
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