Celero hits $3B valuation to scale 2nm coherent digital signal processors

The successful validation of 2nm silicon indicates a shift toward specialized networking hardware capable of handling the massive bandwidth requirements of generative AI. By integrating timing data and error correction directly into the DSP, Celero reduces the physical complexity and cost of high-speed fiber-optic links between and within data centers. As streaming platforms and cloud providers migrate to 1.6T and 3.2T architectures, this technology provides the necessary density to prevent networking from becoming a performance ceiling. Watch for the timeline of initial volume shipments from TSMC to determine when these interconnects will hit commercial data centers.

Celero Communications is entering a coherent DSP market already dominated by established players with deep operator relationships. In June 2026, Ericsson launched its AI in RAN commercial software subscription claiming up to 20% higher downlink throughput across more than 15 live deployments, demonstrating how incumbent vendors are embedding intelligence directly into network hardware rather than relying on separate processing layers. That same architectural philosophy, pushing compute closer to the signal path, mirrors what Celero is attempting at the physical layer with its 2nm coherent DSPs, though Celero targets data center interconnects rather than radio access networks. The competitive landscape for high-speed coherent optics also includes Broadcom, Marvell, and Ciena, all of which have shipped 800G and 1.6T coherent modules to hyperscale operators.

On the business side, Celero's $3 billion valuation reflects investor confidence that AI-driven bandwidth demand will outpace current interconnect capacity. Nokia announced partnerships with AWS and Databricks to build a unified data and cloud control layer for autonomous networks, signaling that network infrastructure vendors are racing to position themselves as essential platforms in the AI value chain. Nokia's Autonomous Network Fabric, which uses agentic AI to orchestrate cross-domain operations, represents the kind of software-defined architecture that will consume ever-greater interconnect bandwidth between data centers. Celero's backers, including CapitalG and Valor Equity Partners, appear to be betting that coherent DSPs sit at a similar chokepoint in the AI infrastructure stack, where demand growth is structural rather than cyclical.

From a technical standpoint, Celero's choice of TSMC's 2nm process node places it at the leading edge of semiconductor manufacturing for networking silicon. Ericsson's AI in RAN trials with T-Mobile US demonstrated roughly 10% better spectral efficiency and up to 15% higher downlink throughput on live 5G Advanced traffic, with full commercial deployment targeted for Q3 2026, showing that specialized silicon can deliver measurable gains even within existing network architectures. For Celero, the analogous benchmark will be power consumption per bit at 1.6T and 3.2T line rates, where the company claims advantages over incumbent coherent DSPs from Broadcom and Marvell. The 2nm node also enables tighter integration of timing recovery and forward error correction blocks, reducing the need for discrete components on the module board and lowering overall system cost for data center operators building next-generation fabric architectures.