Xsight Labs raises $300M at $2.8B valuation for AI networking silicon
Fabless chip designer Xsight Labs has raised $300 million in a new funding round to scale production of its 800-gigabit data processing units and 12.8 Tbps Ethernet switches. The capital will support the company's efforts to provide high-performance, open-architecture networking silicon for AI infrastructure and cloud networks, including compliance with new Ultra Ethernet Consortium standards.
Key Takeaways
- Post-money valuation reached $2.8 billion, a fivefold increase from its 2021 funding round.
- The E1 DPU features 64 Arm Neoverse N2 cores and 800 Gbps throughput on TSMC’s 5nm process.
- The X2 Ethernet switch is currently deployed as the high-speed networking core for Starlink V3 satellites.
- Hardware is validated for the SONiC-DASH Hero 800G benchmark, sustaining 14 million connections per second.
- Funding helps bridge the gap toward Ultra Ethernet 1.0 standards published in June 2025.
Why It Matters
The investment signals a structural shift away from closed, proprietary fabrics toward open-standard Ethernet for AI training and inference. By delivering a programmable data plane that consumes 40% less power than incumbent 12.8 Tbps switches, Xsight addresses the critical power and cooling constraints now limiting hyperscale data center expansion. The design win with SpaceX for Starlink V3 validates the reliability of programmable silicon in extreme orbital environments, suggesting a future where edge networking and space-based AI compute converge. For the streaming ecosystem, this infrastructure upgrade is essential to support the massive real-time data throughput required by distributed inference and global gigabit-connectivity networks. Watch for Tier-1 hyperscaler lab evaluations to convert into high-volume production orders throughout late 2026.
Additional Context
The funding follows the formal launch of the Ultra Ethernet Consortium (UEC) 1.0 specification on June 11, 2025. Per the UEC, the standard defines a new transport protocol designed specifically for AI and High-Performance Computing (HPC), providing remote-memory-access transport and multipath routing to prevent the congestion issues common in general-purpose Ethernet. This industry-wide move toward open fabrics has intensified competition among specialized silicon providers seeking to challenge Nvidia’s dominance in the interconnect layer.
Sector activity has surged consistently through 2025 and early 2026. For example, Enfabrica unveiled its Elastic Memory Fabric System (EMFASYS) in August 2025, claiming its 3.2 Tbps SuperNIC can reduce AI inference costs per token by up to 50% through optimized memory management. Similarly, Axelera AI announced a funding round of more than $250 million in February 2026 to scale its European-designed edge inference hardware for thousands of global customers, citing a fundamental need to solve energy consumption at the edge.
These developments occur against a backdrop where networking is no longer viewed as passive 'plumbing' but as a critical, programmable component of the AI stack. Per Reuters and industry analysts in May 2026, the AI data center networking market is projected to reach $150 billion by 2028. Startups like Xsight and Ethernovia—which raised $90 million in January 2026 for automotive and physical AI networking—are racing to fulfill the manufacturing capacity required as service providers shift from prototyping to full-scale infrastructure build-outs, a trend also seen in AI factory gray failures that impact large-scale deployments, alongside automated Kubernetes cost optimization for AI microservices.
Read full article at unite.ai
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