Socionext develops A14 chiplet to power AI data center scaling
Socionext is developing a high-performance compute chiplet utilizing TSMC’s A14 process node to address demand in AI-focused data center infrastructure. The company plans to tape out a multi-core device in September 2026 to support the development of future AI and accelerated computing SoCs.
Key Takeaways
- Targets a September 2026 tape-out for a multi-core A14-based compute chiplet
- Uses TSMC’s A14 process technology to de-risk high-performance custom silicon development
- Designed to serve as a technology platform for evaluating CPU and xPU scalability in AI workloads
- Initial engagement already involves customers planning A14-based SoCs for hyperscale infrastructure
- Focuses on improving energy efficiency and processing density for data center AI training and inference
Why It Matters
This development signals a shift toward modular chiplet architectures to bypass the physical size limits of monolithic silicon in AI environments. By moving to the A14 node, Socionext provides a path for hyperscalers to maintain performance gains despite the growing thermal and complexity hurdles of large language models. For the streaming industry, this represents the foundational hardware needed to support compute-intensive AI video workflows, including real-time generative upscaling and automated metadata tagging at scale. Watch for the first performance benchmarks of the 2026 tape-out to see how A14 energy efficiency compares to current 2nm and 3nm solutions.
Additional Context
The move to TSMC’s A14 node follows a broader industry transition toward 1.4nm-class manufacturing. Per TSMC at its April 2026 Technology Symposium, the A14 node utilizes NanoFlex Pro technology and is scheduled for high-volume manufacturing in 2028. TSMC reported that A14 is designed to deliver a 15% speed improvement or a 30% power reduction compared to its N2 process, while also increasing logic density by 20%. This aggressive roadmap is a direct response to massive investments from hyperscalers, with Microsoft and Amazon alone committing a combined $180 billion to AI data center builds as of early 2026, according to Mordor Intelligence. Socionext is positioning itself within this capital-intensive ecosystem through its 'Solution SoC' model. In October 2023, the company previously announced a 2nm multi-core CPU chiplet project using Arm Neoverse CSS technology, aiming for engineering samples by 1H 2025. By extending this strategy to the A14 node, Socionext is competing with traditional ASSP vendors by offering purpose-built silicon that optimizes 'Total Cost of Ownership' for specific AI workloads. Per Global Market Insights, hardware is expected to dominate the AI data center market with a 62% share through 2034, as operators shift from general-purpose GPUs to specialized accelerators and chiplet-based 3D-ICs. This technical transition is also driven by physical constraints at the rack level. Many hyperscale facilities are now managing power densities of 30kW to 120kW per rack, according to MarketInsights, necessitating the efficiency gains promised by A14’s nanosheet architecture. Socionext’s 'Flexlets' ecosystem, launched in late 2025, further supports this by allowing customers to mix-and-match process nodes and adopt next-generation interfaces like PCIe Gen7, which are critical for the high-bandwidth data transfers required in modern AI video and compute clusters.
Read full article at newelectronics.co.uk
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