Sandisk and SK hynix release OCP standard for High Bandwidth Flash
Sandisk and SK hynix have published a technical specification for High Bandwidth Flash (HBF) through the Open Compute Project with input from Google and Tenstorrent. This new memory tier aims to bridge the gap between HBM and SSDs to improve the latency of large AI model weight storage in inference infrastructure.
Key Takeaways
- The specification covers host connections, electrical guidelines, packaging, and software operations for stacking NAND flash near AI accelerators.
- Sandisk's first-generation HBF targets include 1.6TB/s read bandwidth and 512GB capacity per 16-die stack, though these are not yet mandated OCP values.
- Initial samples of HBF memory are scheduled for the second half of 2026, with HBF-equipped inference devices expected in early 2027.
- Internal simulations showed HBF performance within 2.2% of unlimited HBM capacity when running the Llama 3.1 405B model.
Why It Matters
HBF addresses the 'memory wall' by providing a higher-capacity, lower-cost tier for storing massive AI model weights that exceed HBM limits. For the streaming industry, this technology is critical for scaling generative AI workloads and real-time metadata processing without the prohibitive costs of HBM-only clusters. By standardizing the interface through OCP, the consortium is attempting to prevent proprietary fragmentation and ensure interoperability across heterogeneous hardware from vendors like Google and Tenstorrent. Watch for the first verified performance data from silicon samples in late 2026 to see if NAND-based latency can truly sustain high-throughput inference.
Additional Context
The release of the HBF specification at the Future of Memory and Storage (FMS) 2026 conference comes as the industry faces severe High Bandwidth Memory (HBM) supply constraints. Per HotHardware, August 2026, HBM prices nearly doubled during the first half of the year, with shortages expected to persist through 2027. This economic pressure has forced a shift toward 'tiered memory' architectures where HBM acts as a 'hot tier' for active compute while HBF serves as a high-density 'warm tier' for parameter storage. This transition is essential as frontier model context windows expand toward 10 million tokens, requiring multi-terabyte caches that are physically impossible to store on HBM alone. Simultaneously, the broader memory market is undergoing what analysts call the 'Great Memory Pivot.' Per TrendForce, early 2026, contract prices for conventional server DRAM surged over 60% as manufacturers reallocated production capacity to HBM and specialized AI storage. This scarcity has downstream effects on the entire data center stack, increasing the cost of standard storage and general-purpose compute. By utilizing Universal Chiplet Interconnect Express (UCIe), HBF aims to bypass the traditional PCIe bus bottlenecks that have historically limited NAND flash performance in near-compute applications. Competitive activity in this space is also accelerating. While Sandisk and SK hynix lead the OCP workstream, NVIDIA recently showcased advancements at FMS 2026 that allow accelerated computing to access storage directly via its 'Vera' platform, per NVIDIA, August 2026. This direct-to-storage architecture mirrors the goals of HBF by reducing data movement latency. As inference costs determine the economic viability of large-scale AI deployments, the success of HBF will depend on whether its 2.5x power efficiency improvement, cited by SK hynix, can offset its naturally higher latency compared to DRAM-based solutions. To manage these complex AI pipeline I/O bottlenecks, infrastructure teams are increasingly looking toward AI infrastructure spending to optimize their data center footprints.
Read full article at xenospectrum.com
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