Nvidia and Synopsys launch agentic AI for 50x faster verification
At DAC 2026, industry leaders including Nvidia, Synopsys, and Intel detailed the industry's shift toward autonomous agentic AI workflows for chip design. The conference highlighted the transition from manual tool-based engineering to system-level, AI-orchestrated workflows, alongside a push for new interoperability standards and consumption-based business models.
Key Takeaways
- Synopsys launched autonomous long-running agents for digital verification and thermal analysis, moving physics simulation into 90% computer-based physical engineering.
- Nvidia made its first DAC appearance, positioning accelerated computing as the essential layer for chains of tools orchestrated by AI agents.
- Intel introduced Package Assembly Design Kits (PADKs) to standardize multi-physics data and prevent mechanical bottlenecks in complex chip stacks.
- Accellera board chairman Lu Dai detailed the draft Functional Safety Language (FSL) 1.0 standard to enable machine-readable traceability across safety-critical supply chains.
Why It Matters
The transition to agentic AI workflows signals a fundamental shift in the semiconductor cost structure, moving from human-expert limitations to compute-bound scalability. For the streaming industry, this acceleration in silicon design directly impacts the development cycle of custom video encoders and high-density compute accelerators needed for next-generation 3D workloads. As EDA vendors explore token-based consumption models, the B2B software market may see a broader pivot away from traditional perpetual licenses toward usage-based billing. Watch for whether the Accellera FSL standard gains adoption among Tier 1 foundry partners, as this will determine the interoperability of autonomous agents across fragmented toolchains.
Additional Context
At the DAC 2026 conference in Long Beach, the shift toward autonomous workflows extended beyond the top-tier vendors to a new wave of specialized startups. Per Forbes in August 2026, firms like ChipAgents and Agentrys are positioning agentic design as a distinct software layer that sits atop traditional tools from Cadence and Synopsys, aiming to reduce manual intervention in RTL design by up to 60%. These startups are developing "agent-native" tools specifically designed for interactive reasoning rather than traditional batch runs, suggesting the primary artifact of future engineering will be the agent itself rather than the chip layout.
Technological synergy was a core focus of the event, particularly in the collaboration between EDA leaders and cloud providers. Per Futurum Group in July 2026, Synopsys recently partnered with Microsoft to launch the first autonomous EDA workflows on the Microsoft Discovery platform, which AMD is currently evaluating for its next-generation AI accelerators. Early tests of this platform indicate a 25% to 40% reduction in debug cycle times, addressing a critical bottleneck in modern high-performance silicon development.
Broader industry standards also reached a milestone during the conference window. Per Accellera in July 2026, the organization released the Functional Safety Language (FSL) 1.0 draft for public review, providing a standardized syntax for FMEDA data exchange. This follows the March 2026 release of the CDC/RDC Standard 1.0, which targets vendor-neutral IP abstraction. Together, these standards form the necessary infrastructure for AI orchestration layer to operate across different vendors without losing critical safety and verification metadata.
Read full article at eetimes.com
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