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Lead the design-for-test and manufacturing-readiness strategy for a neuromorphic silicon program, spanning SoC-level DFT architecture for both synchronous and asynchronous circuits. The role covers scan insertion and compression flows, ATPG test vector generation, pre-silicon validation, and post-silicon bring-up and debug. Requires deep DFT experience from architecture through silicon, including JTAG/BIST and high-volume production readiness.
HQ Belgium·Hybrid