Design Verification Engineer

About the role

The role involves building testbenches, constrained-random tests, and functional checkers to verify interconnect and chassis IP for advanced chip platforms, under senior engineers' guidance. Entry-level candidates need strong digital logic and RTL fundamentals, programming skills in C/C++, Python, or SystemVerilog, and regular use of AI coding assistants. Debugging simulation failures to root cause is a core part of the work.