AI GPU Cache Designer

About the role

This role covers designing the cache subsystem for AI system-on-chip products, including microarchitecture definition, RTL coding in Verilog/SystemVerilog, integration, and simulation to meet power, performance, and area targets. Candidates need substantial ASIC/SoC RTL experience, knowledge of bus protocols such as AXI and AHB, clock-domain-crossing and timing expertise, and scripting skills. The position also involves silicon bring-up and mentoring junior engineers.