Senior DFT Logic Design Engineer

About the role

This role supports foundry customers on DFT and DFM insertion, ATPG validation, and related flows for ASIC designs, including PDK questions and issue resolution. It also involves creating technical training and documentation for block-level and SoC-level work. Candidates need 3+ years of advanced CMOS DFT experience, scripting skills, and US citizenship with clearance eligibility.