CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG)

About the role

Entry-level contract role for a recent diploma graduate in electrical and electronic engineering. The role creates and verifies mask layouts for CPU and SoC chips, including floorplans, power grids, and reliability checks, and requires strong fundamentals and English communication. Familiarity with Unix, VLSI or SystemVerilog is a plus.