Memory Layout Manager

About the role

Leads a team of layout engineers producing memory compiler designs on advanced FinFET and gate-all-around processes, overseeing floorplanning, placement, routing and physical sign-off such as DRC, LVS and EM/IR checks. Requires 15+ years of memory layout experience, advanced-node tape-out history, EDA tool expertise, and scripting skills for automating flows with AI-driven methods.