LVS Runset Development Engineer

About the role

This role develops and validates layout-versus-schematic rule decks for a semiconductor process, working with PDK and foundry teams and keeping results consistent across several EDA verification tools. The engineer debugs LVS issues for design teams, automates flows with scripting, and writes guidelines for layouts. Required: LVS runset experience, SVRF/TVF and Tcl or Python skills.