CPU Senior Floor Plan Engineer

About the role

Defines physical dimensions and floorplans for CPU IP blocks, optimizing die size, pin placement, and metal layer strategy, and integrates dies in packages before tape-out. Collaborates with architecture, clock, logic, and power teams. Requires hands-on Synopsys or Cadence floorplanning and place-and-route experience, plus timing closure and LVS/DRC knowledge at submicron nodes.