Projektmaster (3 Semester): Entwicklung einer transparenten USB-Verlängerung als FPGA-IP-Core

About the role

This three-semester master's project builds a demonstrator for a transparent USB extension as a VHDL IP core on an FPGA. The student analyses USB protocols and transactions, designs the architecture, implements and simulates protocol functions, then integrates and validates the system with real USB devices. The role calls for an electrical engineering or embedded systems background and basic VHDL knowledge.