Volantis has raised $88 million in Series A funding to develop photonic inference chips designed to increase memory bandwidth for AI workloads. The company plans to launch its A-1 inference appliance, which utilizes optical interconnects to support high-parameter models, in 2026.
The shift toward photonic interconnects addresses the physical limitations of copper wiring that currently constrain AI model performance. By extending the range of memory-to-core connections, Volantis allows for a massive increase in memory chiplets per accelerator, which is critical for the low-latency requirements of real-time video and coding agents. This development signals a move away from traditional GPU architectures toward specialized inference hardware as high-parameter models become the industry standard. Watch for the initial A-1 appliance shipments in 2026 to verify if the 10,000 tokens-per-second benchmark holds under real-world data center conditions.
Volantis is positioning its photonic interconnect architecture as a direct answer to the memory bandwidth ceiling that constrains current GPU-based inference. Reuters reported that Volantis is tapping VCSEL technology already present in hundreds of millions of iPhones to eliminate the reach limitations of electrical wires connecting compute and memory chips. While Nvidia's current GPUs can accommodate only eight high-bandwidth memory chips per processor due to copper interconnect distance constraints, Volantis claims its optical approach allows 220 memory chiplets around a single accelerator. The company's founding team includes engineers who previously built the first commercial CoWoS product at Nvidia and early silicon photonics co-packaged optics systems at Ayar Labs, giving them direct experience with the packaging and interconnect challenges they now aim to solve at a different architectural level.
The funding round drew participation from investors with deep AI infrastructure track records. Volantis disclosed that it has raised $97 million in total, with angel backers including Sam Altman, Jeff Dean, and Dylan Patel alongside John Doerr and Naveen Rao. The company's optical fabric design eliminates external lasers and traditional optical fiber, instead using custom integrated micro-VCSELs that draw on the existing gallium arsenide VCSEL supply chain. This avoids indium phosphide supply constraints that have affected other photonic approaches, a deliberate supply-chain decision that could accelerate time-to-volume for the A-1 appliance.
Volantis differentiates its chip-to-memory photonic links from the chip-to-chip optical interconnects that have dominated the photonics market so far. The company's PR Newswire announcement specified that chip-to-memory connections require more than 100 times the data volume of chip-to-chip links over much shorter distances, creating distinct energy and cost requirements. Volantis claims end-to-end link power consumption below one picojoule per bit, and its A-1 system is designed to deliver 10 terabytes of memory with 250 terabits per second of bandwidth in roughly one-third of a standard server rack. The company plans to deliver its first integrated inference engines to customers in 2027, targeting workloads such as coding agents that require both large context windows and high token throughput.
Volantis has raised $88 million in Series A funding to develop photonic inference systems designed to solve AI memory bandwidth bottlenecks. By using optical interconnects instead of copper, the startup's A-1 appliance supports 220 memory chiplets, enabling real-time inference for massive 20-trillion-parameter models and significantly increasing data throughput for AI.
Volantis raised $88 million in its Series A funding round, bringing its total funding to $97 million.
Volantis uses photonic interconnects featuring gallium arsenide VCSELs to extend the range of memory-to-core connections, allowing for significantly more memory chiplets per accelerator than traditional copper wiring.
Volantis plans to deliver its first integrated A-1 inference engines to customers in 2027.
The architecture overcomes the physical limitations of copper wiring, allowing for 220 memory chiplets per accelerator and providing 250 terabits per second of bandwidth, which is 30 times that of current hardware accelerators.
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